Iterative Learning Control Design for Synchronization of Wafer and Reticle Stages

Abstract — This paper presents an iterative learning con-troller (ILC) design technique for synchronization in wafer scanning systems. In wafer scanners, synchronization of the wafer and reticle stages is critical for accurate pattern transfer. For synchronization, a master-slave configuration is used, with the wafer stage acting as the master, and the reticle stage as the slave. Since the scanning process is repetitive, ILC is used to improve tracking performance. However, the coupling between the reticle stage and wafer stage is unidirectional. Hence we propose an ILC scheme that takes into account this structural property of the overall system. A simple design procedure is presented which allows design of the ILC system for the wafer and reticle stages independently. This is done by first designing an ILC controller for the wafer (master) stage, and then using the synchronization error for ILC update for the reticle (slave) stage. Analytic conditions for stability and monotonic error convergence are then discussed. Finally, design and performance of the algorithm is illustrated by implementation on a single degree of freedom wafer stage, and a virtual (computer-simulated) reticle stage. I