Compact low-power 7-bit 2.6 GS/s 65 nm subranging ADCs hardly exceed 300 MS/s since the coarse ADC is CMOS ADC for 60 GHz applications

A 7-bit, 2.6 GS/s time-interleaved analogue-to-digital converter (ADC) for 60 GHz applications is designed and fabricated in 65 nm CMOS. The proposed subranging ADC architecture with time-shifting track-and-hold and two-phase amplification and encoding significantly enhances the speed of individual ADCs and reduces the number of interleaved channels to only four. At 2.6 GS/s sampling rate with a 1.355 GHz input signal, the ADC achieves an effective number of bits of 5.5 bits. Its core occupies 0.3 mm2 chip area and draws 45 mA current from a 1 V supply. Introduction: High-speed (.1 GS/s), medium resolution (6–8 bits) analogue-to-digital converters (ADCs) with low power consumption and small area are key to 60 GHz CMOS transceivers for high data rate wireless communications. Time-interleaved (TI) ADC architecture, which combines multiple low-speed power-efficient subADCs, is con