Exploration plays an important role in the design of high-performance pipelines. We propose an exploration strategy for varying three design parameters by using a performance-constrained component selection and pipelin-ing algorithm on dierent \architectures". The architec-ture is specied manually by using a mix of behavioral and structural constructs, while the component selection and pipelining is performed automatically using our algorithms. Results on two industrial-strength DSP systems, indicate the eectiveness of our strategy in exploring a large design space within a matter of seconds.
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
Single-chip multi-processor embedded system becomes nowadays a feasible and very interesting option....
We present a performance analysis framework that efficiently generates and analyzes hardware archite...
Abstract The use of a realistic component library with multiple implementations of operators, result...
In order to perform high-throughput DSP computations, that are predominantly vector or array based, ...
Abstract: Many embedded and scientific applications are frequently pipelined asynchronously and depl...
This chapter presents guidelines to choose an appropriate exploration algorithm, based on the proper...
Given the constantly growing complexity of multi-core architectures, Design Space Exploration (DSE) ...
Many embedded and scientific applications are frequently pipelined asynchronously and deployed on ar...
In order to satisfy cost and performance requirements, digital signal processing and telecommunicati...
Application-specific multicore architectures are usually designed by using a configurable platform i...
Abstract — This paper shows how a general form of algorithms consisting of a loop with loop dependen...
Many embedded and scientific applications are frequently pipelined asynchronously and deployed on ar...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
This paper formulates and shows how to solve the problem of selecting the cache size and depth of ca...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
Single-chip multi-processor embedded system becomes nowadays a feasible and very interesting option....
We present a performance analysis framework that efficiently generates and analyzes hardware archite...
Abstract The use of a realistic component library with multiple implementations of operators, result...
In order to perform high-throughput DSP computations, that are predominantly vector or array based, ...
Abstract: Many embedded and scientific applications are frequently pipelined asynchronously and depl...
This chapter presents guidelines to choose an appropriate exploration algorithm, based on the proper...
Given the constantly growing complexity of multi-core architectures, Design Space Exploration (DSE) ...
Many embedded and scientific applications are frequently pipelined asynchronously and deployed on ar...
In order to satisfy cost and performance requirements, digital signal processing and telecommunicati...
Application-specific multicore architectures are usually designed by using a configurable platform i...
Abstract — This paper shows how a general form of algorithms consisting of a loop with loop dependen...
Many embedded and scientific applications are frequently pipelined asynchronously and deployed on ar...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
This paper formulates and shows how to solve the problem of selecting the cache size and depth of ca...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
Single-chip multi-processor embedded system becomes nowadays a feasible and very interesting option....
We present a performance analysis framework that efficiently generates and analyzes hardware archite...