Add to ORKGWe describe heavy ion test results for two new SEU tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5microprocess
International audienceThe single event upset (SEU) tolerance of various latch designs in 0.13um CMOS...
We show heavy ion test results of a commercial production-level ReRAM. The memory array is robust to...
The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environmen...
The last few years have seen the development and fabrication of nanoscale circuits at high density a...
This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a ...
Abstract: A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suit...
Upset hardened dual-interlocked cell (DICE) [1] has found an important place in circuits for space a...
The purpose of this testing was to characterize the Texas Instruments SNV54LVC00AW for single-event ...
International audienceThis paper highlights the impact of design on the single-event upset (SEU) sen...
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single ev...
Single-event effect (SEE) test data is presented on the Analog Devices ADV212. Focus is given to the...
Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were designed and man...
Abstract—A new circuit-level single-event upset (SEU) hard-ening approach for high-speed SiGe HBT cu...
We present an independent investigation of heavy-ion single event effect data for the Microsemi RTG4...
Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A ...
International audienceThe single event upset (SEU) tolerance of various latch designs in 0.13um CMOS...
We show heavy ion test results of a commercial production-level ReRAM. The memory array is robust to...
The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environmen...
The last few years have seen the development and fabrication of nanoscale circuits at high density a...
This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a ...
Abstract: A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suit...
Upset hardened dual-interlocked cell (DICE) [1] has found an important place in circuits for space a...
The purpose of this testing was to characterize the Texas Instruments SNV54LVC00AW for single-event ...
International audienceThis paper highlights the impact of design on the single-event upset (SEU) sen...
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single ev...
Single-event effect (SEE) test data is presented on the Analog Devices ADV212. Focus is given to the...
Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were designed and man...
Abstract—A new circuit-level single-event upset (SEU) hard-ening approach for high-speed SiGe HBT cu...
We present an independent investigation of heavy-ion single event effect data for the Microsemi RTG4...
Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A ...
International audienceThe single event upset (SEU) tolerance of various latch designs in 0.13um CMOS...
We show heavy ion test results of a commercial production-level ReRAM. The memory array is robust to...
The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environmen...