Abstract: In this paper, an improved floorplanning algorithm, named the floorplanning algorithm based on particle swarm optimization algorithm nesting simulated annealing to optimize the floorplans (PSO-SA-NoC), has been proposed with simulations conducted to verify this algorithm. The simulation results are compared with the original Simulated Anneal-ing-NoC. The results show that the CPU’s process time of the PSO-SA-NoC algorithm decreased by 35.39%. The packet transmission latency reduces 4.05 % in the average case and 83.3 % in the best case respectively. The throughput improves 1.72 % in the average case and 10.57 % in the best case respectively
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three...
Mapping of IP(Intellectual Property) cores onto NoC(Network-on-Chip) architectures is a key step in ...
In the paper we describe P-medians searching algorithm for Three-dimensional (3D) Network-on-Chip (N...
Abstract: Nowadays, three-dimensional network-on-chip (3D NoC) with its shorter global interconnects...
Constant necessity of improving performance has brought the invention of 3D chips. The improvement i...
Abstract—The conventional simulated annealing with some random gen-eration mechanism using the seque...
Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-...
Abstract:- In this paper, a rectilinear-based congestion-driven floorplanning algorithm is presented...
Floorplanning is an important physical design step for hierarchical, building-block design methodolo...
Quality of task scheduling is critical to define the network communication efficiency and the perfor...
Power optimization is an important part of network-on-chip(NoC) design. This paper proposes an impro...
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the ...
AbstractIn the past, shared bus based architecture was used as a communication architecture in SoC. ...
none5Three dimensional integration is a promising approach for reducing the form factor of chips. Sc...
Multi-core System-on-Chips (SoCs) are a promising research area due to their improved speed (due to ...
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three...
Mapping of IP(Intellectual Property) cores onto NoC(Network-on-Chip) architectures is a key step in ...
In the paper we describe P-medians searching algorithm for Three-dimensional (3D) Network-on-Chip (N...
Abstract: Nowadays, three-dimensional network-on-chip (3D NoC) with its shorter global interconnects...
Constant necessity of improving performance has brought the invention of 3D chips. The improvement i...
Abstract—The conventional simulated annealing with some random gen-eration mechanism using the seque...
Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-...
Abstract:- In this paper, a rectilinear-based congestion-driven floorplanning algorithm is presented...
Floorplanning is an important physical design step for hierarchical, building-block design methodolo...
Quality of task scheduling is critical to define the network communication efficiency and the perfor...
Power optimization is an important part of network-on-chip(NoC) design. This paper proposes an impro...
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the ...
AbstractIn the past, shared bus based architecture was used as a communication architecture in SoC. ...
none5Three dimensional integration is a promising approach for reducing the form factor of chips. Sc...
Multi-core System-on-Chips (SoCs) are a promising research area due to their improved speed (due to ...
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three...
Mapping of IP(Intellectual Property) cores onto NoC(Network-on-Chip) architectures is a key step in ...
In the paper we describe P-medians searching algorithm for Three-dimensional (3D) Network-on-Chip (N...