IST/INESC-ID

Abstract — This paper presents a new scheme for designing residue generators using threshold logic. This approach is based on the periodicity of the series of powers of 2 taken modulo kn ±2. In addition, a new algorithm is proposed to obtain a new set of partitions which are more advantageous in terms of area and delay for the presented topology. Experimental results in the analized range of k and n show that new proposed circuits using the novel partitioning are 70 % faster and provide area savings of 64%, when compared with similar circuits using the partitioning methods presented to date. Keywords- generator modulo A, residue number systems, binary-to residue number systems converter, threshold logic. I