Programmable Flexible Cores for SoC Applications

Today’s embedded systems integrate digital and analog technologies into a single chip, known as System-on-Chip (SoC), in order to achieve increased performance, system relia-bility, and reduction in packaging and test costs. As fabrication technology advances and processes shrink, design costs escalate due to increasing system complexity, and challeng-ing integration and verification tasks. Part of the digital circuitry of an SoC is comprised of fixed digital logic blocks, but another part is often custom designed, and may benefit from redesigns and updates, or may have a dual use (regular and test mode, for example). This is possible when reconfigurable digital blocks exist, that are capable of supporting different digital functions after silicon fabrication. Reconfigurable logic reduces design risk and any design error can be corrected quickly and inexpensively. Inside an SoC, the space left after placing the analog circuitry and other large Intellectual Propery (IP) cores is very often non-rectangular. I propose using a non-rectangular core of standard cell based reconfigurable logic to fill that space, thereby adding to the final prod-uct the advantage of reconfiguration with a potentially short design cycle. The goal of th