An empirical three-dimensional crossover capacitance model for multilevel interconnect vlsi circuits

Abstract—We develop an empirical model for the crossover ca-pacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry param-eters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance de-fined on a same layer. The model agrees well with the numerical field solver (with a 6.7 % root-mean-square error) and measure-ment data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 m and wire thickness down to 0.15 m. The model is useful for VLSI design and process optimization. Index Terms—Closed-form models, crossover capacitance, mul-tilevel interconnects, VLSI circuits. I