Faster qualification of 193-nm resists for 100-nm development using photo cell monitoring

The development of 100-nm design rule technologies is currently taking place in many R&D facilities across the world. For some critical layers (gate, contact, local interconnect), the transition to 193-nm resist technology has been required to meet this leading edge design rule. As with previous technology node transitions, the materials and processes available are undergoing changes and improvements as vendors encounter and solve problems. The initial implementation of the 193-nm resist process did not meet the photolithography requirements of some IC manufacturers due to very high Post Exposure Bake (PEB) temperature sensitivity and consequently high wafer to wafer CD variation. The photoresist vendors have been working to improve the performance of the 193-nm resists to meet their customer’s requirements. Characterization of these new resists needs to be carried out prior to implementation in the R&D line. Initial results on the second-generation resists evaluated at Cypress Semiconductor (San Jose, CA) showed better CD control compared to the earlier resist with comparable Depth of Focus (DOF), Exposure Latitude, Etch Resistance, etc. In addition to the standard lithography parameters, resist characterization needs to include defect density studies. It was found that the new resist process with the best CD control, resulted in the introduction of orders of magnitude higher yield limiting defects at Gate (micro bridging), Contact (deformed/closed contacts) and Local Interconnect. The defect data were shared with the resist vendor and within days of the discovery the resist vendor was able to pinpoint the sourc