Hardware Acceleration of Monte-Carlo Integration in Finance

This thesis describes FPGA-accelerated Monte-Carlo integration us-ing adaptive stratified sampling. Monte-Carlo integration can be used to determine the value of integrals that have no closed form so-lution. In this work, the FPGA-accelerated design is used to deter-mine the price of different types of financial options. The considered options are a basket option, an Asian option and a barrier option. Stratified sampling is implemented with the recursive general pur-pose algorithm MISER. First, a parallel software implementation of MISER is developed. Next, the integrand independent part of the software is moved into reconfigurable hardware. Finally, the different options are priced in FPGAs by developing hardware implementa-tions of the integrand for each option. The integrands are compiled into a deep pipeline, producing one function evaluation per cycle at 150 MHz. The FPGA-accelerated design requires up to 4200 times less execution time to achieve the same accuracy as a software imple-mentation using the GSL library running on an Intel i7-4770 CP