Available online:http://internationaljournalofresearch.org / P a g e | 944 FPGA Power Reduction by Mux based Clock Gating Considering a Logic Architecture Student: Naresh Kumar R (12841D5703) Guide: Mr.: K SatishBabu (M.Tech) Associate Professor

Guarded evaluation is a power reduction technique that involves identifying subcircuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not “observable ” at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for applicationspecific integrated circuits (ASICs); in this paper, we apply the technique to field-programmable gate arrays (FPGAs). In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The primary challenge in guarded evaluation is in determining the specific conditions under which a subcircuit’s inputs can be held constant without impacting the larger circuit’s functional correctness. We propose a simple solution to this problem based on discovering gating inputs using “noninverting ” and “partial noninverting ” paths in a circuit’s AND-inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity on average by as much as 32 % and 25 % for 6-input look-up table (6-LUT) and 4