Design of 1-Kb eFuse OTP Memory IP with Reliability Considered

Abstract—In this paper, we design a 1-kb OTP (One-time programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the non-programmed eFuse is reduced from 728 µA to 61 µA when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 kΩ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier). Index Terms—eFuse, OTP, electro-migration, variabl