1Fanout Optimization under a Submicron Transistor-Level Delay Model

In this paper we present a new fanout optimization algorithm which is particularly suitable for digital cir-cuits designed with submicron CMOS technologies. Restricting the class of fanout trees to the so-called bipolar LT-trees, the topology of the optimal fanout tree is found by means of a dynamic programming algorithm. The buffer selection is in turn performed by using a continuous buffer sizing technique based on a very accurate de-lay model especially developed for submicron CMOS processes. The fanout trees can distribute a signal with arbitrary polarity from the root of the tree to a set of sinks with arbitrary required time, required minimum signal slope, polarity and capacitive load. These trees can be constructed to maximize the required time at the root or to minimize the total buffer area under a required time constraint at the root. The performance of the algorithm shows several improvements with respect to conventional fanout optimization methods. More precisely, individ-ual fanout trees are typically built with 60 % and 10 % lower area and delay, respectively, while the accuracy of calculated arrival times and signal slopes at the sinks have a typical agreement of 5 % with SPICE simulations. On the other hand, the area and delay improvements for entire circuits are 34 % and 4%, respectively. These results are obtained for a standard library which contains tapered and non tapered buffers with different strengths. I