A framework for open tiled manycore system-on-chip

Manycore System-on-Chip include an increasing amount of process-ing elements and have become an important research topic for improve-ments of both hardware and software. While research can be conducted using system simulators, prototyping requires a variety of components and is very time consuming. With the Open Tiled Manycore System-on-Chip (OpTiMSoC) we aim at building such an environment for use in our and other research projects as prototyping platform. This paper describes the project goals and aspects of OpTiMSoC and summarizes the current status and ideas. 1 Motivation & Project Goals Multicore System-on-Chip have become dominant in research and industry as high-performance and power-efficient processing platforms. With increasing amounts of processing elements the tile organization is a popular way to orga-nize the elements of such a platform. Those platforms base on Network-on-Chip with a regular organization, often a mesh. Processing elements, memories and I/O devices are connected to this interconnect as tiles. This allows for platform creation by replicating these basic tiles to larger platforms. Some examples for tiled platforms are Tilera’s processors or Intel’s “Single Chip Cloud Computer”. Many aspects of such platforms are currently in the focus of research, for example system design aspects, communication-to-computation coupling, co-herency and consistency issues, programming of future massively parallel plat-forms and many more. Research of improvements of future manycore system-on-chip is mainly per-formed using system simulation approaches, where a variety of tools exist. Nev-ertheless when it comes to prototyping, hardware architects rely on a platfor