Process Optimization and Downscaling of a Single Electron Single Dot Memory

This paper presents the process optimization of a single electron nano-flash electron memory. Self aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nano-wires. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nano-wire shape) have been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor two. This point has been previously confirmed by the realization of single electron memory devices. Index Terms Process modeling, flash memories, non volatile memories, quantum dot, single-electron device, device scaling, scaling limits, silicon on insulator technology (SOI). I