In this paper we propose an algebra of synchronous scheduling interfaces which combines the expres-siveness of Boolean algebra for logical and functional behaviour with the min-max-plus arithmetic for quantifying the non-functional aspects of synchronous interfaces. The interface theory arises from a realisability interpretation of intuitionistic modal logic (also known as Curry-Howard-Isomorphism or propositions-as-types principle). The resulting algebra of interface types aims to provide a general setting for specifying type-directed and compositional analyses of worst-case scheduling bounds. It covers synchronous control flow under concurrent, multi-processing or multi-threading execution and permits precise statements about exactness an...
Interworkings can be considered as a synchronous variant of Message Sequence Charts. In this paper w...
Abstract—In this article, we study several relevant alge-braic frameworks to define synchronous lang...
A fundamental timing analysis problem in the verification and synthesis of interface logic circuitry...
We propose synchronous interfaces, a new interface theory for discrete-time systems. We use an appli...
Abstract. We propose synchronous interfaces, a new interface theory for discrete-time systems. We us...
We propose synchronous interfaces, a new interface theory for discrete-time systems. We use an appli...
This thesis develops a general framework for symbolic analysis of real-time systems based on process...
In industry, discrete models can be used to describe and analyze a class of event driven systems. Th...
This book proposes a unified mathematical treatment of a class of 'linear' discrete event systems, w...
Interface Algebra for Analysis of Hierarchical Real-Time Systems Complex real-time embedded systems ...
SynchronousBoolean relations can represent sequential don't care information in synchronous sys...
Complex real-time embedded systems can be developed using component based design methodologies. Timi...
This paper addresses the question of producing modular sequential imperative code from synchronous d...
Recently we proposed a mathematical framework offering diverse models of computation and a formal fo...
RR version = http://hal.inria.fr/hal-00780521/enInternational audienceIn this paper, we propose an e...
Interworkings can be considered as a synchronous variant of Message Sequence Charts. In this paper w...
Abstract—In this article, we study several relevant alge-braic frameworks to define synchronous lang...
A fundamental timing analysis problem in the verification and synthesis of interface logic circuitry...
We propose synchronous interfaces, a new interface theory for discrete-time systems. We use an appli...
Abstract. We propose synchronous interfaces, a new interface theory for discrete-time systems. We us...
We propose synchronous interfaces, a new interface theory for discrete-time systems. We use an appli...
This thesis develops a general framework for symbolic analysis of real-time systems based on process...
In industry, discrete models can be used to describe and analyze a class of event driven systems. Th...
This book proposes a unified mathematical treatment of a class of 'linear' discrete event systems, w...
Interface Algebra for Analysis of Hierarchical Real-Time Systems Complex real-time embedded systems ...
SynchronousBoolean relations can represent sequential don't care information in synchronous sys...
Complex real-time embedded systems can be developed using component based design methodologies. Timi...
This paper addresses the question of producing modular sequential imperative code from synchronous d...
Recently we proposed a mathematical framework offering diverse models of computation and a formal fo...
RR version = http://hal.inria.fr/hal-00780521/enInternational audienceIn this paper, we propose an e...
Interworkings can be considered as a synchronous variant of Message Sequence Charts. In this paper w...
Abstract—In this article, we study several relevant alge-braic frameworks to define synchronous lang...
A fundamental timing analysis problem in the verification and synthesis of interface logic circuitry...