Implementation of a Fast Sign Detection Algoritm for the RNS Moduli Set {2

, 2 N}, N =16,64 is illustrated. This algorithm allows parallel implementation and completes the implementation with simply modulo 2n additions. This unit can be implemented using one carry save adder, one comparator, one carry generation unit and post processing unit. The results of this algorithm confirm that the area and delay are reduced com-pared to mixed radix conversion and Chinese reminder theroms. This algorithm is implemented using verilog language tool in Xilinx 13.2 version