REDUCE POWER CONSUMPTION FOR DIGITAL CMOS CIRCUITS USING DVTS ALGORITHAM

The Power consumption of large scale integrated circuits increasing with each generation which becomes a serious design issue. This paper proposed a generalized power tracking algorithm that reduces power directly by dynamic control of supply voltage and body bias. The DVTS algorithm-(Dynamic Voltage and threshold scaling algorithm) save the leakage power during active mode of the circuit. Total active power can be minimized by dynamically adjusting Vdd and Vth based on circuit operating conditions such as temperature, workload, and circuit architecture. The power saving method of DVTS is similar to that of the Dynamic VDD Scaling (DVS) scheme, which adaptively changes the supply voltage depending on the current workload of the system. For a digital circuit, it is possible to trade off dynamic and sub threshold leakage power by balancing between Vdd and Vth to maintain performance