DESIGN AND IMPLEMENTATION BIT LEVEL OPTIMIZATION OF ADDER-TREES FOR MULTIPLE CONSTANT MULTIPLICATION FOR EFFICIENT FIR FILTER

The most area and power consuming arithmetic operation in high-performance circuits like Finite Impulse Response (FIR), multiplication is one. There are different types of multipliers to reducing the cost and effective parameters in FIR filter design. Among those this paper use modified Wallace multiplier in the fir design. The structural adders and delay elements occupies more area and consumes power in this form so it was a reason to forward the proposed method. In prior FIR filters design with low cost effective results will done with the carry skip additions. Along with that the proposed method modified Wallace multiplier based fir filter is also designed in this paper to make the FIR filter design is suitable for low power applications