AN EFFICIENT IMPLEMENTATION OF POWER AND AREA OPTIMIZED ON-CHIP NETWORK COARSE-GRAINED PROCESSOR

Coarse Grained Arrays (CGAs) with run-time reconfigurability play an important role in accelerating reconfigurable computing applications. It is challenging to design On-chip Communication Networks (OCNs) for such CGAs with dynamic run-time reconfigurability whilst satisfying the tight budgets of power and area for an embedded system. This project presents a silicon-proven design of a circuit-switched OCN fabric with a dynamic path-setup scheme capable of supporting an embedded coarse-grained processor array. The paper involves design of a RISC core processor and simulating it. A Reduced Instruction Set Compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor while executing the instruction along with reduction of area(gate count) and power consumption. The RISC architecture follows the philosophy that one instruction should be performed every cycle. This work presents the design and implementation of a 32 bit RISC soft core processor intended for computer architecture introduction considered to be an effective solution for computer comprehension. The idea of this project was to create a microprocessor as a building block in VHDL than later easily can be included in a larger design. The processor gets the data from the serial device uart which can reduce the transmission cost. It will be useful in systems where a problem is easy to solve in software. However at a high level of complexity it is easier to implement the function along with reduced power consumption and area (gate count). In this project XILINX ISE 12.3i is used for logical verification and further synthesizing