A NEW APPROACH TO HIGH EFFICIENCY LOGIC TRANSISTOR BASED SLEEPY SRAM USING 130 NM TECHNOLOGY

The integrated circuit design has important role of various parameters are considering for design the circuit. The important parameters are power and delay. The different tools are used to perform the operation. However, here the combinational circuit designed by using different logic. As a substitution by using low power design techniques the power consumption is being reduced. Here the low power logic used is sleepy approach. In the sleep approach, an additional “sleep” PMOS transistor is placed between VDD and the pull-up network of a circuit and an additional “sleep ” NMOS transistor is placed between the pull-down network and GND. The CMOS leakage current to the process level can be decreased by using sleepy keeper technique. The advantages in this technique are ultra-low leakage with dual Vth, state-saving, less area penalty and faster than other techniques like sleepy stack approach, sleep, Zig Zag