The complexity of large-scale multiprocessors has burdened the design and verification process making complexity-effective func-tional verification an elusive goal. We propose a solution to the verification of complex systems by introducing an abstracted veri-fication environment called Raven. We show how Raven uses stan-dard C/C++ to extend the capability of contemporary discrete-event logic simulators. We introduce new data types and a diagnos-tic programming interface (DPI) that provide the basis for Raven. Finally, we show results from an interconnect router ASIC used in a large-scale multiprocessor.
Abstract—The verification of a system-on-chip is challenging due to its high level of integration. M...
Verification of chip multiprocessor memory systems re-mains challenging. While formal methods have b...
Abstract—The goal of System Level Formal Verification (SLFV) is to show system correctness notwithst...
A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of milli...
In this paper we present the real-time verification and analysis tool RAVEN. RAVEN is developed for ...
Abstract. A number of impressive verification tools and techniques have been developed over the last...
Formal verification has become an important task in the design of systems. Techniques like symbolic ...
As the world increasingly depends on complex systems to transfer messages, store our data, and contr...
We propose a new simulation-based technique for verifying applications running within a large hetero...
After caches, most transistors in a modern microprocessor are devoted to wide data-paths. Due to per...
The Verification methodology of modern processor designs is an enormous challenge. As processor desi...
The paper presents a sequence of three projects on design and formal verification of pipelined and s...
We report on our experience with a new test generation language for processor verification. The veri...
The goal of System Level Formal Verification (SLFV) is to show system correctness notwithstanding un...
International audienceWe propose a new simulation-based technique for verifying applications running...
Abstract—The verification of a system-on-chip is challenging due to its high level of integration. M...
Verification of chip multiprocessor memory systems re-mains challenging. While formal methods have b...
Abstract—The goal of System Level Formal Verification (SLFV) is to show system correctness notwithst...
A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of milli...
In this paper we present the real-time verification and analysis tool RAVEN. RAVEN is developed for ...
Abstract. A number of impressive verification tools and techniques have been developed over the last...
Formal verification has become an important task in the design of systems. Techniques like symbolic ...
As the world increasingly depends on complex systems to transfer messages, store our data, and contr...
We propose a new simulation-based technique for verifying applications running within a large hetero...
After caches, most transistors in a modern microprocessor are devoted to wide data-paths. Due to per...
The Verification methodology of modern processor designs is an enormous challenge. As processor desi...
The paper presents a sequence of three projects on design and formal verification of pipelined and s...
We report on our experience with a new test generation language for processor verification. The veri...
The goal of System Level Formal Verification (SLFV) is to show system correctness notwithstanding un...
International audienceWe propose a new simulation-based technique for verifying applications running...
Abstract—The verification of a system-on-chip is challenging due to its high level of integration. M...
Verification of chip multiprocessor memory systems re-mains challenging. While formal methods have b...
Abstract—The goal of System Level Formal Verification (SLFV) is to show system correctness notwithst...