Fractional-N Frequency Synthesizer Design Using PLL Design Assistant and CppSim Programs,‖ July 2008

A new methodology for designing fractional-N frequency synthesizers and other phase locked loop (PLL) circuits is presented. The approach achieves direct realization of the desired closed loop PLL transfer function given a set of user-speci¯ed parameters and automatically calculates the corre-sponding open loop PLL parameters. The algorithm also accomodates nonidealities such as parasitic poles and ze-ros. The entire methodology has been implemented in a GUI-based software package, which is used to verify the approach through comparison of the calculated and simu-lated dynamic and noise performance of a third order §-¢ fractional-N frequency synthesizer