Clock-tree power optimization based on RTL clock-gating

As power consumption of the clock tree in modern VLSI de-signs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reduc-ing clock power based on clock gating. We present a method-ology that, starting from an RTL description, automatically generates a set of constraints for driving the construction of the clock tree by the clock synthesis tool. The methodology has been fully integrated into an industry-strength design flow, based on Synopsys DesignCompiler (front-end) and Cadence Silicon Ensemble (back-end). The power savings achieved on some industrial examples show that, when the size of the circuits is significant, savings on the power con-sumption of the clock tree are up to 75 % larger than those achieved by applying traditional clock gating at the clock inputs of the RTL modules of the designs