Abstract – This paper presents a new recovery scheme for dealing with short-to-long duration transient faults in combinational logic. The new scheme takes earlier into account results of concurrent error detection (CED) mechanisms, and then it is able to perform shorter recovery latencies than existing similar strategy. The proposed scheme also requires less memory resources to save input contexts of combinational logic blocks. In addition, this work also proposes a taxonomy of CED techniques. It allows pointing out which are the necessary recovery resources as well as identifying which are the types of CED mechanisms that can be used with the new recovery scheme of this paper. The effectiveness of the proposed scheme was evaluated through ...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded proc...
A new data capturing technique for a potentially coupled bus of lines is proposed that always accomm...
International audienceThis paper presents a new recovery scheme for dealing with short-to-long durat...
Abstract – This work reveals additional timing difficulties by which concurrent error detection (CED...
International audienceThis work introduces a simulation-based method for evaluating the efficiency o...
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are ...
We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic....
Abstract — In any circuit that comprises the logic gates, there is possibility of occurrence of fail...
This paper presents a concurrent error detection tech-nique targeted towards control logic in a proc...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0167-9317This paper presents vario...
Recent years, there is an increasing interest of integrating mixed-criticality functionalities onto ...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
Although today’s the trends of technology scaling is going to bring higher performance computer syst...
Abstract—In this work we present a novel fault-tolerant circuits design method. It combines time and...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded proc...
A new data capturing technique for a potentially coupled bus of lines is proposed that always accomm...
International audienceThis paper presents a new recovery scheme for dealing with short-to-long durat...
Abstract – This work reveals additional timing difficulties by which concurrent error detection (CED...
International audienceThis work introduces a simulation-based method for evaluating the efficiency o...
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are ...
We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic....
Abstract — In any circuit that comprises the logic gates, there is possibility of occurrence of fail...
This paper presents a concurrent error detection tech-nique targeted towards control logic in a proc...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0167-9317This paper presents vario...
Recent years, there is an increasing interest of integrating mixed-criticality functionalities onto ...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
Although today’s the trends of technology scaling is going to bring higher performance computer syst...
Abstract—In this work we present a novel fault-tolerant circuits design method. It combines time and...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded proc...
A new data capturing technique for a potentially coupled bus of lines is proposed that always accomm...