1 PWM Optimized Power MOSFETs for Low-Voltage DC/DC Conversion

Designers of low-voltage dc-to-dc converters have two main concerns: reducing size and reducing losses. As a way of reducing size, designers are increasing switching frequencies. But the result has been reduced converter efficiency. To minimize losses, MOSFET manufacturers have generally focused on lowering on-resistance. But the results have not been optimal for dc-to-dc conversion designs, since gate charge and switching speed issues have been largely ignored. The dominant losses associated with MOSFETs were once conduction losses, but this is no longer the case. Vishay Siliconix’s new family of PWM optimized MOSFETs has been designed to give the highest efficiency available for a given on-resistance in switching applications such as dc-to-dc conversion. These new devices provide a very low gate charge per unit of on-resistance, in addition to fast switching times. The result is reduced gate drive and crossover losses, allowing designers of dc-to-dc converters to simultaneously reduce the design footprint and increase efficiency. MOSFET Losses A simplistic model of power loss in a MOSFET used in a dc-to-dc converter (Figure 1) can be calculated if we know the RMS, the current through the MOSFET, the duty cycle, the gate voltage, and the rDS(on) of the MOSFET. This model can then be used to compare the efficiency of designs using Vishay Siliconix’s new PWM optimized MOSFETs versus conventional and low-threshold power MOSFETs. The equation that defines the losses associated only with on-resistance and the gate drive is: P I2RMS rDS(on)VGS TJ D Q gVG