FPGA

Abstract- Multiplication of two bits produces an output which is twice that of the original bit. It is usually needed to truncate the partial product bits to the required precision to reduce area cost. Fixed-width multipliers, a subset of truncated multipliers, compute only n-most significant bits (MSBs) of the 2n-bit product for n × n multiplication and use extra correction/compensation circuits to reduce truncation errors. Truncated multipliers provides significant improvements in area, delay, and power. The proposed method finally reduces the number of full adders and half adders during the tree reduction. The output is in the form of LSB and MSB. Finall