GLOBAL JOURNAL OFENGINEERINGSCIENCE ANDRESEARCHES

A built-in self repair analyzer with the optimal repair rate for memory arrays with redundancy. The existing techniques use depth first search using a stack and a finite-state machine. Instead, our formulation for the circuit allows us to use the parallel prefix algorithm, it can be configured in various ways to meet area and test time requirements. The total area of our infrastructure is dominated by the number of content addressable memory entries to store the fault addresses, and it only grows quadratically with respect to the number of repair elements. The linear feedback shift register used to count the next state and also requires high transitions in BIST architecture. The content addressable memory is used to identify the fault address to store in must-repair analyzer. The proposed methods using the bit swapping linear feedback shift register to reduce both the transition and the power consumption. It requires only a single test, even in the worst case. By performing the must-repair analysis during the test, it selectively stores fault addresses, and the final analysis to find a solution is performed on the stored fault addresses. The infrastructure is also extended to support various types of word-oriented memories