Design and Implementation of 4Kb SRAM Array Controller with Optimized Memory Decoders at 28nm

Abstract:Optimization of SRAM (Static Random Access Memory) array design can be done at three domains namely bit cell optimization, sense amplifier optimization and memory decoder optimization. In this paper, we focused on memory decoder optimization. The objective of the paper is to design speed and power efficient memory decoder structure and to implement 4Kb SRAM array controller. We compared four NAND gate based decoder structures at TSMC 28nm technology and OR style NAND decoder structure is found to be efficient. We also implemented 4Kb SRAM array controller which is a byte accessible using binary decoder tree. All the logics have been designed using Cadence Virtuoso schematic editor and simulated using Spectre simulator with operating voltage of 0.9 V