OPTIMIZATION OF DISTRIBUTED ARITHMETIC BASED FIR FILTER

Abstract:The VLSI design industry has grown rapidly during the last few decades. The complexity of the applications increases day by day due to which the area utilization increases. The tradeoff between area and speed is an important factor. The main focus of continued research has been to increase the operating speed by keeping the area and memory utilization of the design as low as possible. We present the parallel DA approach in which LUT decomposed into small units to enhance the operating speed and to reduce the critical path