REVIEW ON ERROR DETECTION AND CORRECTION

Abstract — Majority logic decodable codes are suitable for memory applications because of their capability to correct large number of errors. Another method of decodable logic is Majority Logic Decoder/Detector which reduces not only the decoding time but also memory access time as well as area utilization. Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes are used for error correction, because of their fault-secure detector capability. EG-LDPC codes are used to avoid high decoding complexity. The application of a similar technique to a class of Euclidean geometry low density parity check (EG-LDPC) codes that are one step majority logic decodable. The obtained results show that the method is also effective for EG-LDPC codes. The proposed design of error detection and correction will coded using VHDL, verified and synthesize on Modelsim and Xilinx FPGA respectively