AREA AND POWER EFFICIENT CMOS ADDER DESIGN BY HYBRIDIZING PTL AND GDI TECHNIQUE SUVASINI SB

Abstract- In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling factors. Leakage power accounts for an increasingly larger portion of total power consumption in deep submicron technologies. Recently, in technology the power density has increased due to combination of higher clock speed, smaller process geometries and scaling factors, layout structure and greater functional integration. As results static power consumption is becoming more dominant state. This is a challenge for the CMOS integrated circuit designers. However the integrated CMOS designers do have a few methods which they can use to reduce this static power consumption. Since, these methods have some drawbacks. To attain lowest static power consumption one has to sacrifice design area and circuit performance. In this paper we proposed a new method to reduce static power in the CMOS VLSI circuit using dual stack approach without being penalized in area requirement and circuit performance. Index Terms- dual stack approach, static power saving technique, stack effect, static power reduction