8T Double-Ended Read-Decoupled SRAM

Abstract-Scaling of SRAM cell beyond 65-nm poses a serious threat to the stability of the cell and is a cause of major concern for the upcoming technologies. Due to random dopant fluctuation (RDF) and other process parameter variations, the cell turns out to be unstable. In this paper, an 8T (8-Transistor) SRAM cell is proposed which offers enhanced data stability during read operation. While reading, the voltage level of the ‘0 ’ holding node does not increase and thus a near ideal butterfly-curve is achieved, which is crucial to design a robust SRAM cell. In 16-nm technology node, the read static noise margin or read SNM (RSNM) as high as 159 mV at supply voltage (VDD) of 600 mV is achieved by the proposed cell. Therefore, the cell is 4.18 × more stable than the standard 6T SRAM cell during read operation and has 1.87 × shorter delay than the standard 6T SRAM cell at the same voltage. Also the proposed cell offers 4.15 × improvements in write delay. All these are achieved at a marginal penalty of write static noise margin (WSNM) 1.07 × compared to standard 6T