VLSI IMPLEMENTATION OF FULL DUPLEX, FSM BASED GIGABIT ETHERNET MAC

Abstract — The communication network is analogous to the neural system of the human body for any embedded system. It carries data and control signals to various parts of the system. Hence, a high speed communication system is the need of the hour so that it does not become the bottleneck of the system‘s performance. Of all the available communication systems, Ethernet stands out as the most common network communication protocol. But due to advances in the technology, the primitive Ethernet could no longer match the processing speed of the new systems. Therefore, we need to improve the performance of the Ethernet. The evolution to Gigabit Ethernet improved the speed from few Megabits to one Gigabit and thus improved the performance of the whole embedded system. Increasing the bus width of the Ethernet is one way to increase the speed, but this comes with the overhead of encoders and decoders to be used and also increases the chance of causing interference. Another way is to use a clock with high speed, thus keeping the bus width low and avoiding the overheads and interference probabilities. This project selects a 125 MHz clock and 8 bit bus width for constructing a Gigabit Ethernet MAC on FPGA board. Finite state machine technique is used to construct the same. The project is coded using VHDL in Xilinx 14.1 and simulations are done in ISim simulator. The project was implemented on Spartan 3XC3S20