Design & Analysis of High-Performance Floating-point Fused Multiply-add with Reduced Latency

Abstract: Floating-point unit is an integral part of any modern microprocessor. The fused multiply add (FMA) operation is important in many scientific and engineering applications. With the advancement in FPGA architecture latency has been the important focus of attention in order to improve performance. To improve the performance, two single-precision operations can be performed concurrently with one double-precision data path, which is very useful in multimedia and even scientific applications. Moreover, to reduce the additional area costs for supporting two single-precision operations in parallel, multiple double-precision units, i.e., the multiplier, shifter and adder, are reused as much as possible. In addition, in case of FADD instructions, the multiplier in the first stage is bypassed and kept in stable mode, which can significantly improve fused addition instruction performance and lower power consumption. The paper claims an estimated 15-20 % reduction in latency as compared to a conventional fused multiply add (FMA)