POWER AND PERFORMANCE EFFICIENT TOPOLOGICALLY COMPRESSED DUAL VDD FLIP FLOP

The very low power and high speed dual VDD Flip Flop (FF) is proposed in this paper. The power reduction has achieved by introducing dual VDD technique with two different supply voltages as Vdd1 and Vdd2. The small number of MOS transistors are connected to clock signal, reduces drastic leakage power consumption, and the smaller no of transistor count makes the cell area equals to conventional FFs. In addition, fully static full-swing operation makes the cell tolerant of supply voltage and input slew variation. With dual VDD, topologically compressed flip flop gives 82.72 % improvement over power, delay and power delay product and the nontopologically compressed flip flop gives only 30.79 % improvement as compared with conventional flip flops. An experimental chip design is carried out by 90 nm CMOS technology