Applying Cryptographic Acceleration Techniques to Error Correction

Abstract. Modular reduction is the basic building block of many public-key cryptosystems. BCH codes require repeated polynomial reductions modulo the same constant polynomial. This is conceptually very similar to the implementation of public-key cryptography where repeated mod-ular reduction in Zn or Zp are required for some fixed n or p. It is hence natural to try and transfer the modular reduction expertise developed by cryptographers during the past decades to obtain new BCH speed-up strategies. Error correction codes (ECCs) are deployed in digital com-munication systems to enforce transmission accuracy. BCH codes are a particularly popular ECC family. This paper generalizes Barrett’s mod-ular reduction to polynomials to speed-up BCH ECCs. A BCH(15, 7, 2) encoder was implemented in Verilog and synthesized. Results show sub-stantial improvements when compared to traditional polynomial reduc-tion implementations. We present two BCH code implementations (regu-lar and pipelined) using Barrett polynomial reduction. These implemen-tations, are respectively 4.3 and 6.7 faster than an improved BCH LFSR design. The regular Barrett design consumes around 53 % less power than the BCH LFSR design, while the faster pipelined version consumes 2.3 times more power than the BCH LFSR design.