Buying AES Design Resistance with Speed and Energy

Abstract. Fault and power attacks are two common ways of extracting secrets from tamper-resistant chips. Although several protections have been proposed to thwart these attacks, resistant designs usually claim sig-nificant area or speed overheads. Furthermore, circuit-level countermea-sures are usually not reconfigurable at runtime. This paper exploits the AES ’ algorithmic features to propose low-cost and low-latency protec-tions. We provide Verilog and FPGA implementation details. Using our design, real-life applications can be configured during runtime to meet the user’s needs and the system’s constraints.