Abstract. The study of asynchronous circuit behaviors in the presence of component and wire delays has received a great deal of attention. In this paper, we consider asynchronous circuits whose components can be any non-deterministic sequential machines of the Moore type, and describe a formal model for these circuits and their behaviors under the inertial delay model. We model an asynchronous circuit C by a network N of modules with delays associated with its components and/or wires. We compute the behavior of N assuming arbitrary inertial delays in the modules, and take this behavior to be correct. We define N to be strongly delay-insensitive if its behavior remains correct in the presence of arbitrary stray delays, where correctness is d...
In Part I of this paper, a larger asynchronous circuit was regarded as successfully simulating a sma...
AbstractThis paper shows how synchrony conditions can be added to the purely asynchronous model in a...
An asynchronous unit delay is an n-input n-output sequential circuit in which the present value of t...
AbstractConsider a network N constructed from a set of modules interconnected by wires. Suppose that...
Consider a network N constructed from a set of modules interconnected by wires. Suppose that there i...
Abstract. In the study of asynchronous designs most authors use the interleaving model of concurrenc...
Although the theory of asynchronous circuits (fates back to the early 1950s, considerable progress h...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is ...
Concurrent and distributed behaviour encompasses a wide range of ever evolving phenomena and feature...
Two categorical models of asynchronous circuits are presented. The first uses the bicategory of span...
AbstractDelays of signal propagation inherent in the wires interconnecting the logical elements of a...
A new definition of semi-modularity to accommodate relative timing constraints in self-timed circuit...
An asynchronous unit delay (A.U.D.) is an asynchronous sequential circuit in which, the present valu...
Two trends are of major concern for digital circuit designers: the relative increase of interconnect...
: Quasi-delay-insensitive (QDI) circuits are those whose correct operation does not depend on the de...
In Part I of this paper, a larger asynchronous circuit was regarded as successfully simulating a sma...
AbstractThis paper shows how synchrony conditions can be added to the purely asynchronous model in a...
An asynchronous unit delay is an n-input n-output sequential circuit in which the present value of t...
AbstractConsider a network N constructed from a set of modules interconnected by wires. Suppose that...
Consider a network N constructed from a set of modules interconnected by wires. Suppose that there i...
Abstract. In the study of asynchronous designs most authors use the interleaving model of concurrenc...
Although the theory of asynchronous circuits (fates back to the early 1950s, considerable progress h...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is ...
Concurrent and distributed behaviour encompasses a wide range of ever evolving phenomena and feature...
Two categorical models of asynchronous circuits are presented. The first uses the bicategory of span...
AbstractDelays of signal propagation inherent in the wires interconnecting the logical elements of a...
A new definition of semi-modularity to accommodate relative timing constraints in self-timed circuit...
An asynchronous unit delay (A.U.D.) is an asynchronous sequential circuit in which, the present valu...
Two trends are of major concern for digital circuit designers: the relative increase of interconnect...
: Quasi-delay-insensitive (QDI) circuits are those whose correct operation does not depend on the de...
In Part I of this paper, a larger asynchronous circuit was regarded as successfully simulating a sma...
AbstractThis paper shows how synchrony conditions can be added to the purely asynchronous model in a...
An asynchronous unit delay is an n-input n-output sequential circuit in which the present value of t...