Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits

Abstract—Random telegraph noise (RTN) is one of the critical re-liability concerns in nanoscale circuit design, and it is important to consider the impact of RTN on the circuits ’ temporal performance. This paper proposes a framework to evaluate the RTN-induced performance degradation and variation of digital circuits, and the evaluation results show that RTN can result in 54.4 % degradation and 59.9 % variation on the circuit delay at 16nm technology node. Power supply tuning and gate sizing techniques are investigated to demonstrate the impact of such circuit-level techniques on mitigating the RTN effect. Index Terms—Random telegraph noise, Performance degradation, Mitigation technique I