Fpga accelerated parallel sparse matrix factorization for circuit simulations

Abstract. Sparse matrix factorization is a critical step for the circuit simulation problem, since it is time consuming and computed repeatedly in the flow of cir-cuit simulation. To accelerate the factorization of sparse matrices, a parallel CPU+FPGA based architecture is proposed in this paper. While the pre-processing of the matrix is implemented on CPU, the parallelism of numeric factorization is explored by processing several columns of the sparse matrix si-multaneously on a set of processing elements (PE) in FPGA. To cater for the requirements of circuit simulation, we also modified the Gilbert/Peierls (G/P) algorithm and considered the scalability of our architecture. Experimental re-sults on circuit matrices from the University of Florida Sparse Matrix Collec-tion show that our architecture achieves speedup of 0.5x-5.36x compared with the CPU KLU results