Add to ORKGA wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMO
A 100-MHz-2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is pres...
none4siWe present an integer-N all-digital frequency-locked loop (ADFLL) suitable for dynamic voltag...
[[abstract]]This paper presents a wide-range CMOS reference clock generator with a dynamic duty cycl...
Abstract—A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is ...
Abstract — In high-speed data transmission applications, such as double data rate memory and double ...
Abstract — A system clock with a 50 % duty cycle is demanded in high-speed data communication applic...
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is don...
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is don...
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is don...
[[abstract]]A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses s...
[[abstract]]A high-resolution all-digital duty-cycle corrector (ADDCC) with a novel pulse-width dete...
Abstract ಧ In this paper, a low-power delay-recycled all-digital duty-cycle corrector (ADDCC) is pre...
Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐ske...
In high-speed data transmission applications such as double data rate memory and double sampling ADC...
The design and characterization results of a high-resolution phase-shifter are presented. The phase-...
A 100-MHz-2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is pres...
none4siWe present an integer-N all-digital frequency-locked loop (ADFLL) suitable for dynamic voltag...
[[abstract]]This paper presents a wide-range CMOS reference clock generator with a dynamic duty cycl...
Abstract—A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is ...
Abstract — In high-speed data transmission applications, such as double data rate memory and double ...
Abstract — A system clock with a 50 % duty cycle is demanded in high-speed data communication applic...
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is don...
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is don...
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is don...
[[abstract]]A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses s...
[[abstract]]A high-resolution all-digital duty-cycle corrector (ADDCC) with a novel pulse-width dete...
Abstract ಧ In this paper, a low-power delay-recycled all-digital duty-cycle corrector (ADDCC) is pre...
Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐ske...
In high-speed data transmission applications such as double data rate memory and double sampling ADC...
The design and characterization results of a high-resolution phase-shifter are presented. The phase-...
A 100-MHz-2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is pres...
none4siWe present an integer-N all-digital frequency-locked loop (ADFLL) suitable for dynamic voltag...
[[abstract]]This paper presents a wide-range CMOS reference clock generator with a dynamic duty cycl...