We introduce a novel class of massively parallel processor architectures called invasive tightly-coupled processor arrays (TCPAs). The presented processor class is a highly parameterizable template, which can be tailored before run-time to ful-fill costumers ’ requirements such as performance, area cost, energy efficiency. These programmable accelerators are well suited for domain-specific computing from the areas of signal, image, and video processing as well as other streaming pro-cessing applications. To overcome future scaling issues (e. g., power consumption, reliability, resource management, as well as application parallelization and mapping), TCPAs are inherently designed in way that they support self-adaptivity and resource-awarenes...
Power and energy efficiency are important challenges for the High Performance Computing (HPC) commun...
Emerging trends in embedded systems and applications need high throughput and low power consumption....
As we continue to be able to put an increasing number of transistors on a single chip, the answer to...
This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly c...
Abstract—In this paper, we present an ultra low power design for a class of massively parallel archi...
In this paper we give a fresh look to Coarse Grained Reconfigurable Arrays (CGRAs) as ultralow power...
International audienceIn this paper we give a fresh look to Coarse Grained Reconfigurable Arrays (CG...
There is a growing trend to use coprocessors to offload and accelerate domain-specific applications ...
The Smith Waterman algorithm is used to perform local alignment on biological sequences by calculati...
Complex media applications are becoming increasingly common on general-purpose systems such as deskt...
Workshop on Reconfigurable Computing 2022International audienceCoarse-grained reconfigurable archite...
The scaling of silicon technology has been ongoing for over forty years. We are on the way to commer...
Abstract—Energy-efficiency has emerged as a major barrier to performance scalability for modern proc...
To help shrink the programmability-performance efficiency gap, we discuss that adaptive runtime syst...
As power has become the pre-eminent design constraint for future HPC systems, computational efficien...
Power and energy efficiency are important challenges for the High Performance Computing (HPC) commun...
Emerging trends in embedded systems and applications need high throughput and low power consumption....
As we continue to be able to put an increasing number of transistors on a single chip, the answer to...
This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly c...
Abstract—In this paper, we present an ultra low power design for a class of massively parallel archi...
In this paper we give a fresh look to Coarse Grained Reconfigurable Arrays (CGRAs) as ultralow power...
International audienceIn this paper we give a fresh look to Coarse Grained Reconfigurable Arrays (CG...
There is a growing trend to use coprocessors to offload and accelerate domain-specific applications ...
The Smith Waterman algorithm is used to perform local alignment on biological sequences by calculati...
Complex media applications are becoming increasingly common on general-purpose systems such as deskt...
Workshop on Reconfigurable Computing 2022International audienceCoarse-grained reconfigurable archite...
The scaling of silicon technology has been ongoing for over forty years. We are on the way to commer...
Abstract—Energy-efficiency has emerged as a major barrier to performance scalability for modern proc...
To help shrink the programmability-performance efficiency gap, we discuss that adaptive runtime syst...
As power has become the pre-eminent design constraint for future HPC systems, computational efficien...
Power and energy efficiency are important challenges for the High Performance Computing (HPC) commun...
Emerging trends in embedded systems and applications need high throughput and low power consumption....
As we continue to be able to put an increasing number of transistors on a single chip, the answer to...