An accurate MIMO fading channel simulator using a compact and high-throughput reconfigurable architecture

Abstract—This article presents an ultra-compact and high-throughput reconfigurable architecture for implementing an efficient fading channel simulator that supports a relatively large number of propagation paths. To closely reflect actual radio signal propagation conditions, we used a recently improved Rayleigh and Ricean fading channel model based on the sum-of-sinusoids technique. The improved model is optimized for a significantly more compact hardware implementation. To achieve a fast fading variate generation rate with much less hardware and no significant loss in accuracy, instead of generating fading samples directly, the new scheme first generates fading samples at a lower rate using a time-multiplexed datapath that can be fit into a small fraction of a field-programmable gate array (FPGA). In the second step, the simulator uses a compact multiplication-free linear interpolator to produce the fading samples between variates generated at a lower rate. Implementing a 64-path fading channel simulator on a Xilinx Virtex-4 XC4VLX200-11 FPGA requires only 13044 (14%) of the configurable slices, 10 (2%) of the block memories, and one (1%) of the dedicated DSP blocks, while generating 64 × 191 million complex-valued fading samples per second. The simulated paths can be readily combined to form high path count models for multiple-input multiple-output systems as well as frequency-selective channels. Index Terms—Rayleigh fading, Ricean fading, sum-of-sinusoids model, hardware-accelerated simulation, MIMO chan-nel model. I