He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Version accepted for publication in the Springer Journal of Signal Processing Systems Abstract The end of Dennardian scaling in advanced technologies brought about new architectural templates to overcome the so-called utilization wall and provide Moore’s Law-like performance and energy scaling in embedded SoCs. One of the most promising templates, architectural heterogeneity, is hindered by high cost due to the design space explosion and the lack of effective exploration tools. Our work provides three contribu-tions towards a scalable and effective methodology for design space exploration in embedded MC-SoCs. First, we present the He-P2012 architecture, augmenting the state-of-art STMicroelectronics P2012 platform with het-erogeneous shared-L1 coprocessors called HW processing elements (HWPE). Second, we propose a novel method-ology for the semi-automatic definition and instantiation of shared-memory HWPEs from a C source, support-ing both simple and structured data types. Third, we demonstrate that the integration of HWPEs can provide significant performance and energy efficiency benefits on a set of benchmarks originally developed for the ho-mogeneous P2012, achieving up to 123x speedup on the accelerated code region (∼98 % of Amdahl’s law limit) while saving 2/3 of the energy. This work was supported by the EU Projects P-SOCRATES (FP7-611016) and PHIDIAS (FP7-318013)