A Wide-Range All-Digital Duty-Cycle Corrector with Output Clock Phase Alignment in 65nm CMOS technology

Abstract—A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is presented in this paper. The proposed ADDCC can correct the duty-cycle error of the input clock to 50 % duty-cycle. The frequency range of the input signal is 250MHz to 1GHz. In addition, the duty-cycle range of the input signal is from 20 % to 80%. The proposed ADDCC is implemented in a standard performance 65nm CMOS process. The power consumption is 0.79m