Single FPGA Simulator for Geometric MIMO Fading Channel Models

Abstract — We propose a compact and fast hardware channel simulator for the baseband verification and prototyping of multiple-input multiple-output (MIMO) wireless communication systems. The simulator accurately and efficiently implements models of both single-bounce and multiple-bounce geometric propagation conditions. Fading samples are generated at a low rate, comparable to the Doppler frequency, and then interpolated to match the desired sample rate. Bit-true simulations verify the accuracy of the implemented simulator. As an example, when implemented on a Xilinx XC5VLX110 field-programmable gate array (FPGA), our 4 × 4 MIMO geometric fading channel simulator occupies only 6.6 % of the configurable slices while generating more than 16 × 324 million samples per second. The geometric MIMO fading channel simulator is well suited for use in a FPGA-based error rate performance verification system. I