A Reference-Less Single-Loop Half-Rate Binary CDR

Abstract—This paper proposes a half-rate single-loop reference-less binaryCDR that operates from 8.5Gb/s to 12.1Gb/s (36 % cap-ture range). The high capture range is made possible by adding a novel frequency detection mechanism which limits the magnitude of the phase error between the input data and the VCO clock. The proposed frequency detector produces three phases of the data, and feeds into the phase detector the data phase that minimizes the CDR phase error. This frequency detector, implemented within a 10 Gb/s CDR in Fujitsu's 65 nm CMOS, consumes 11 mW and im-proves the capture range by up to 6 when it is activated. Index Terms—Burst-mode CDR, clock and data recovery, cycle-slipping, frequency detection, gated VCO. I