Validation of functional processor descriptions by test generation

Abstract. Microprocessor design deals with many types of specifications: from functional models (SystemC or proprietary languages) to hardware description languages such as VHDL or Verilog. Functional descriptions are key to the development of new processors or System On Chips at STMicroelectronics. In order to reduce validation effort and meet aggressive time to market requirements, it is essential to discover all potential defects as early as possible in the functional model, which is at the center of the design methodology. In this paper we address the problem of automatic generation of high quality testsuites for microprocessor func-tional models. We introduce an overview of a software tool based on constraint solving techniques which analyzes the control flow of the initial description in order to generate tests for each path. We achieve better path coverage than typical hand-written assembler testsuites. STM7, a STMicroelectronics micro-controller, has been used to check this novel test generation method. Com-posed of about 700 various instructions and 3000 lines of SystemC-like code, it is complex enough to assess the performances of our solution