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Keywords: Process variation Thread-level redundancy Chip Multiprocessor an ch t act be first formulate the above scheduling problem as a 0–1 programming problem to maximize the system rrors, ture In rticles cell o through parallel execution is generally regarded as the most prom-ising architecture for future high performance computing, which typically couples two adjacent cores statically with glue logics in between in the literature. As depicted in Fig. 1, communication channels and buffer queues are used to bind two adjacent cores to support thread redundant execution. We call it CMP with Static Core Coupling (CMP-SCC) architecture in this paper. CMP-SCC is much similar to Paceline structure as introduced in [4]. Process variation [2,17,18] is another important issue that can-not be ignored during system and architecture design phases, as precise control of manufacturing process becomes extremely difficult, if not impossible. For CMPs, within-die variation causes individual core frequency or leakage characteristics to diffe